Synopsys hiring "Intern-Technical" for B.E/B.Tech/M.Tech graduates, Bangalore-May 2014

POSTED DATE:31 May 2014

COMPANY NAME: Synopsys

COMPANY PROFILE:                            Synopsys is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, IP and services used in semiconductor design and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and FPGA solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. 

WEBSITE DETAILS: http://www.synopsys.com

FIELD OF WORKING: Core/Technical JOB ROLE: Intern-Technical JOB REQ NUMBER: 6744BR

SALARY OFFERED: Best in industry

JOB LOCATION: Bangalore

LAST DATE: ASAP

REQUIRED QUALIFICATION: B.E/B.Tech/M.Tech

EXPERIENCE REQUIRED: Freshers

CANDIDATE PROFILE: The candidate must have completed Bachelors degree in electronics/ Electrical engg with minimum 70% or 7.0 CGPA. Partial or full completion of MS/MTech is preferable with overall grades of 7.0 or above. Candidates with good problem solving skills and kknowledge of HDL such as Verilog with strong concepts in OOPs and C++.  Exposure to HVL Languages such as SystemVerilog/Vera/SpecmanE is highly preferable. Aptitude to work in VLSI Verification domain is a must and only those who are willing to put it extra effort and take up technical challenges need apply .

JOB DESCRIPTION: The selected intern candidate will be part of the IP verification/ VIP team in Solutions Group, Synopsys , India and be based at Bangalore. The focus area of activities would be Verification/ VIP/ Test Environment development in System Verilog/ Vera in a VMM environment in one of the following domain :USB3/USB2/Ethernet/MIPI The intern will be  taken through hands-on training in Verification methodologies such as VMM and in the respective domain. Subsequent to training, the nature of work would be on the following lines: Understanding product architecture for VIP or Test environment, coding in one of the HVL such as System Verilog, Verification of the blocks that are coded, understanding and implementing functional coverage infrastructure. It will involve closely working as part of the product development team.

APPLY MODE: Online

HOW

To Apply:          Interested and eligible candidates apply this position in online as soon as possible(before the link expires).

To Apply : Click here Click => https://sjobs.brassring.com/1033/ASP/TG/cim_jobdetail.asp?jobId=1015915&PartnerId=25235&SiteId=5359 link to Apply Online.